1. Field of the Invention
The present invention relates to equipment and a method for molding a semiconductor device. More particularly, the present invention relates to a mold die for molding a chip array, molding equipment including the same, and a method for molding a chip array.
2. Description of the Related Art
Molding processes are typically used for sealing semiconductor chips after wire-bonding has been completed, by encapsulating the chips and the bonding wires with a chemical resin. The molding process is typically performed in a mold die, which is incorporated into a larger molding apparatus. A typical mold die comprises a pot for holding the mold resin, a cavity block for defining one or more cavities, a paddle, a runner block, and a gate block for defining and controlling a gate through which the resin may enter a cavity. A typical molding apparatus may include 2, 4, 6, or more separate cavity blocks symmetrically disposed in a mold die and connected to a common pot through one or more runner blocks and gate blocks.
Molding processes can be broadly categorized into single molding processes and chip-array molding processes, depending on the number of semiconductor chips loaded in one cavity block. While only a single semiconductor chip is loaded in each cavity in a single molding process, a plurality of semiconductor chips are loaded to form a matrix in each cavity in a chip-array molding process. Since a chip-array molding process typically requires a greater amount of mold resin than a single molding process, the mold die gate for single molding processes may be relatively narrow, while the mold die gate for chip-array molding process will tend to be considerably wider to increase the rate at which the mold resin enters the cavity.
Chip-array molding processes, which are highly productive and which can be much more economical than a single molding processes, are widely used. Chip-array molding processes are typically utilized more frequently in conjunction with certain packaging methods, such as multi-chip package (MCP) and system in package (SIP) configurations, but as the demand for chip-scale packages (CSP) increases, chip-array molding processes are becoming more widely used.
FIG. 1A shows a schematic arrangement of a cavity and a gate of a conventional mold die for molding a chip array with FIG. 1B illustrating a cross-sectional view taken along line I-I′ of FIG. 1A.
Referring to FIGS. 1A and 1B, a mold die for molding a chip array includes a cavity block 100 and a gate block 110. Although not shown in the drawings, a runner block is typically disposed adjacent the gate block 110 for defining a resin flow path between the pot and the gate block
A recessed surface is provided in the cavity block 100 to define the cavity 105 that will be filled with mold resin that flows from the pot, through the runner block and through the gate 115 during the molding process. A plurality of semiconductor chips 12 on which the wire-bonding process has been completed may be arranged in cavity 105. The semiconductor chips 12 may be attached to, for example, a printed circuit board (PCB) or other suitable substrate 10. In a typical mold die for molding a chip array, a regular array of, for example, four, six, or nine semiconductor chips are attached and wire-bonded to a printed circuit board 10 using conventional assembly processes before being placed in the cavity 105.
As shown in FIG. 1A, the gate 115 of the gate block 110 included in the mold die for molding a semiconductor array has a width only slightly less than the width of a side of the cavity 105 to allow the cavity to be filled more easily with mold resin before the mold resin is hardened. FIGS. 2A through 2D illustrate a series of sequential images from a simulation of mold resin filling a cavity of a conventional mold die for molding a chip array having an arrangement of a cavity 105 and a gate 115 as illustrated in FIG. 1A.
Referring to FIGS. 2A through 2D, as the mold resin, which is entering the cavity 105 at a substantially constant rate, meets a first semiconductor chip 12 disposed in the first row, its flow is impeded by the front surface of the semiconductor chip. In other words, the mold resin starts to flow more slowly at a portion where a semiconductor chip 12 is disposed (see FIGS. 2B and 2D) within the cavity 105 and tends to separate and flow around the semiconductor chip.
FIG. 3 is a diagram of a unit chip of a chip array indicating in more detail the general direction of the flow(s) of the mold resin as it fills the cavity of FIG. 1A. As illustrated in FIG. 3, the semiconductor chips 12 may be a type of multi-chip package (MCP) having an upper semiconductor chip 12a and a lower semiconductor chip 12b. The semiconductor chips and/or the substrate typically include bonding pads 16 and wire-bonding terminals 18 with bonding wires 20 providing electrical connection between designated bond pads and terminals.
As illustrated in FIG. 3, when mold resin is injected perpendicularly to one side of the semiconductor chip 12, the resin will slow as it meets the front side chip surface and will begin to flow around the lateral sides of the chip. Thus, while the mold resin flows past the lateral side of the semiconductor chip 12 at a relatively high rate, its flow past the front side is at a relatively low rate. This results in a flow of the mold resin bypassing the entire semiconductor chip 12 or, in a case of a stack-type multi-chip package (MCP), the entire upper semiconductor chip 12a. Mold resin that has bypassed the semiconductor chip(s) and reached a portion of the cavity where no semiconductor chip 12 is disposed starts again to flow again in all directions at the same rate. As a result, the bypass flow of the mold resin around both lateral sides of the semiconductor chip 12 tend to meet at a rear central region A of the semiconductor chip 12.
In a typical molding process, a sweeping phenomenon occurs. That is, the bonding wires 20 tend to be displaced in the flow direction due to the friction of flow of mold resin flowing past the bonding wire. The sweeping phenomenon is inevitable as mold resin flows past bonding wires with the sweeping force being generally proportional to the length and orientation of the bonding wires exposed to the flow.
However, in semiconductor packages, such as MCP and SIP, where a plurality of semiconductor chips are assembled, the length of the bonding wires 20 tends to increase. As the length of the bonding wires 20 increases, the sweeping forces tend to become more severe and the occurrence of failures increases. Accordingly, when an MCP or SIP is used, the position, spacing and orientation of the bonding wires should be designed with consideration of the sweeping phenomenon in order to provide increased resistance to such failures. Then, as long as the sweeping forces are generally within the limits anticipated by the design, shorts between adjacent wires and the resultant failures will be reduced.
Unlike cases in which the sweeping forces are applied in only one direction, the chip-array molding process must typically be carried out with sweeping forces applied in a plurality of directions while still accommodating demanding requirements for the positioning of bonding wires, the pitch between adjacent bonding wires, and the like. As described above with regard to FIG. 3, the mold resin flowing along both sides of the semiconductor chip 12 will tend to meet behind the rear side of the semiconductor chip 12. As a result, on the rear side of the semiconductor chip 12, bonding wires 20 on either side of region A are swept in opposite directions that tend to force the bonding wires toward each other.
Accordingly, if the positioning of the bonding wires and the pitch between wires are designed with consideration of sweeping forces that are applied in only one direction, the bonding wires, when swept in opposite directions, may be forced into contact with each other near the region A, thus causing a short. In particular, because the length of bonding wires is relatively large in MCP and SIP mounting techniques, the risk of such wire shorts may be increased relative to other package configurations.
To prevent the formation of such shorts, the positions of wires may be changed or the pitch between the wires may be increased. However, as these remedial methods must be incorporated into the layout and a fabrication process of an integrated circuit, they are difficult and complicated to achieve while still maintaining the desired device dimensions.